MEMS Resettable Circuit Breaker and Switch for DC-DC Voltage Converters

These circuit breaker cantilevers use silicon dioxide for temperature compensation.

Resettable circuit breaker cantilevers use silicon dioxide (SiO2) for temper ature compensation. The compressive stress in the SiO2 causes the cantilever to bow upwards 400 μm after release. In the DC-DC voltage converter, the gap between the electrodes is 1.4 μm. After release, the cantilevers are stuck down. A short-loop experiment was conducted to better understand the cantilever behavior by omitting the contact metal and SiO2 layers from test cantilevers.

(a) A SEM image of the DC-DC Voltage Converter after release, and (b) an optical profilometer image of chip-style D9 illustrating acceptably flat cantilevers on shorter cantilevers.
Silicon-only cantilevers were fabricated with the existing mask set. The silicon-on-insulator (SOI) wafer (cantilever wafer) was patterned with the release and the metal3 (bond metal) masks. The release mask defines the handle silicon area that is etched to allow the cantilever to move. The metal3 layer defines the bonding area to a double-sided polished (DSP) wafer. The DSP wafer, or substrate wafer, was patterned with the indent (3.1 μm deep) and metal1 (bond metal).

The SOI and DSP wafers were bonded together using Au-Au thermal compression bonding at 360 oC with a force of 800N for 45 minutes. Following the bonding, the handle silicon was etched using deep reactive ion etching (DRIE). To release the cantilevers, the buried oxide on the SOI wafer was etched using reactive ion etch (RIE). The figure shows a scanning electron microscope (SEM) image and an optical profilometer image of the MEMS switch for a DC-DC voltage converter. The smaller cantilevers (<1000 μm) have a slight downward bow that is due to thermal effects and permanent deformation of the metals during bonding, or a thermal and charging effect from the reactive ion etch. The larger cantilevers bow enough to cause contact with the bottom electrode. The optical profilometer data suggest that the smaller cantilevers have an acceptable gap of 2-3 μm between the cantilever and the bottom electrode. Using these data, a Rev B full wafer fabrication process was developed.

For the Rev B process, the indent is increased by 2 μm to 5 μm. For the resettable circuit breaker, tensile deposited silicon nitride is used for thermal compensation in place of compressive thermally grown SiO2. The tensile stress of the silicon nitride film causes the cantilever to bow downward or come in contact with the bottom electrode, closing the circuit for the MEMS circuit breaker. For the DC-DC voltage converter, thinner (200 nm) SiO2 is used as contact isolation material at each cantilever tip. This balances the tensile stress from metal with compressive stress from oxide, keeping the cantilever from touching the bottom electrode. The fabrication of Rev B wafers is currently in progress.

This work was done by Susana Stillwell, Sunny Kedia, Weidong Wang, Shinzo Onishi, and Scott Samson of SRI International for the Office of Naval Research. For more information, download the Technical Support Package (free white paper) at www.defensetechbriefs.com/tsp  under the Electronics/Computers category. ONR-0016



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MEMS Resettable Circuit Breaker and Switch for DC-DC Voltage Converters

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Defense Tech Briefs Magazine

This article first appeared in the December, 2010 issue of Defense Tech Briefs Magazine (Vol. 4 No. 6).

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Overview

The document is a Monthly Status Report for January 2010, detailing the progress of the Power MEMS Development project, specifically under contract N00014-09-C-0252, sponsored by the Office of Naval Research. Prepared by Dr. John Bumgarner, the report covers activities from January 1 to January 31, 2010.

The report highlights the development of silicon-only cantilevers and MEMS (Micro-Electro-Mechanical Systems) devices, including resettable circuit breakers and switches for DC-DC voltage converters. The fabrication process involved using silicon-on-insulator (SOI) wafers, which were patterned with release and bonding masks. The bonding of SOI and double-sided polished (DSP) wafers was achieved through Au-Au thermal compression bonding at 360ºC. Following bonding, the handle silicon was etched to allow cantilever movement, and buried oxide was removed to release the cantilevers. The report notes that smaller cantilevers exhibited a slight downward bow, potentially due to thermal effects during bonding or etching, while larger cantilevers had a more significant bow that could lead to contact with the bottom electrode.

The report also discusses the Rev B full wafer fabrication process, which included increasing the indent depth from 3.1 μm to 5 μm and replacing compressive thermally grown SiO2 with tensile deposited silicon nitride for thermal compensation. This change aimed to mitigate issues related to cantilever bowing.

In addition to cantilever development, the report outlines progress in positron trapping and storage, detailing the fabrication of MEMS-based trap structures for RF trapping of electrons. The first electron trap prototype was completed, although challenges were encountered with the surface resistance of atomic layer deposition (ALD) ZnO, which was higher than expected due to thermal gradients during deposition. Despite this, SEM analysis indicated good charge dissipation, and modifications to the deposition recipe were suggested for future iterations.

Financially, the report provides an overview of the program's budget status, indicating that current funding is sufficient for the fiscal year, with cumulative expenses reported. Overall, the document reflects significant advancements in MEMS technology development, addressing both technical challenges and financial management within the project.