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Memory-Based, Structured, Application-Specific Integrated Circuit (ASIC)

This methodology enables the design of ASICs that include on-chip memory, as well as multiple processing cores, networks-on-chips, and I/O modules.

For air, space, and ground-based systems, there is a clear need for high-performance, lightweight, low-power, highly reliable computing on data-intensive applications. A data-intensive application is one in which there is a very large volume of data, which is often accessed in irregular patterns. Yet, despite the fact that application-specific integrated circuits (ASICs) are becoming more memory-intensive, commodity memory and ASIC design and manufacturing technologies are still on divergent paths.

This work explored the use of regular fabrics for lowering the barrier to using commodity memory technology for memory-intensive ASICs. A regular fabric is a system of circuits and design methodologies that best utilizes the simple, regular patterns that can be reliably printed for logic, memory, and analog circuits with a single, compatible, subwavelength lithography setup. In particular, results show that laying out logic circuitry on regular grids that are based on memory array spacing can substantially improve the manufacturability of memory-intensive ASIC designs. Regular fabrics are especially conducive to ebeam lithography, where electron beams transcribe patterns directly to the silicon wafer, without the use of photolithographic masks. Because of this, regular fabrics provide a path for cost-effective, low-volume production by reducing mask cost.

Given the base technology for implementing memory-intensive ASICs that regular fabric provides, a further challenge is giving architects the tools to evaluate tradeoffs and explore the range of possible designs for complex, heterogeneous ASIC designs. Such designs may include many processor cores, interconnection networks, I/O components, and multiple varieties of memory, including 3D stacks or quilts. To address this challenge, both midrange and high-level tools were developed for modeling power, area, and timing in multi- and many-core systems.

Figure 2. Dielectric Constant of the Polymers under study at different temperatures. The dielectricconstant of BOPP is shown at 95 °C, and that of the other three polymers is shown at 200 °C, along with the data at 30 °C for comparison.
High-level analysis tools can reduce design cycle time, cost, and risk by enabling design space exploration for area, speed, and power for multicore, memory-intensive systems. System-level tools that use simple heuristic and analytic models, as well as “midrange” tools that run in conjunction with a standard architectural simulator, are both necessary. The midrange tool, named McPAT (Multi-core Power, Area and Timing), uses circuit-level models coupled with statistics from an architectural simulation to obtain fairly accurate predictions. The high-level tools use simpler models, but permit rapid exploration and characterization of a broad design space.

Unlike prior tools, which were tightly integrated with specific performance simulators, McPAT uses an XML interface to decouple the architectural simulator from the power, area, and timing analysis, so that it can be readily used with a variety of simulators. McPAT’s power models account for dynamic power, subthreshold leakage, and gate leakage, as well as short-circuit power, using calculated timing information to determine the interval when both the pull-up and pull-down devices are conducting. It is also the first processor power modeling environment to include both power gating and clock gating, as well as support for P-state and C-state power management schemes. In providing these capabilities, McPAT supports architects in exploring a broad design space for future multicore and many-core systems.

This work was done by Jay Brockman, Peter Kogge, and Michael Niemier of the University of Notre Dame; and Larry Pileggi of Carnegie Mellon University for the Air Force Research Laboratory. For more information, download the Technical Support Package (free white paper) at www.defensetechbriefs.com/tsp  under the Electronics/Computers category. AFRL-0140

Topics:
Education and training Electronic equipment Electronics & Computers Integrated circuits People and personalities Research and development Simulation and modeling Simulators Tools and equipment
This Brief includes a Technical Support Package (TSP).
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Memory-Based, Structured, Application-Specific Integrated Circuit (ASIC)

(reference AFRL-0140) is currently available for download from the TSP library.

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    Defense Tech Briefs Magazine

    This article first appeared in the December, 2009 issue of Defense Tech Briefs Magazine (Vol. 3 No. 6).

    Read more articles from this issue here.

    Read more articles from the archives here.

    Overview

    The document titled "Memory-Based Structured Application Specific Integrated Circuit (ASIC) Study" presents a comprehensive analysis of innovative methodologies for designing memory-based ASICs. Authored by researchers from the University of Notre Dame, the report is structured around three major project studies: the evaluation of Structured ASICs (SASICs) using regular fabrics, the development of a midrange framework for modeling complex multicore chips, and the creation of a high-level modeling framework.

    The report begins with an introduction to the challenges faced in the design of memory-intensive systems, emphasizing the need for efficient design methodologies that can reduce costs and risks associated with the design cycle. It outlines the approach taken in the study, which includes high-level design space exploration to optimize area, speed, and power.

    Key findings highlight the effectiveness of high-level analysis tools in significantly reducing design cycle time and costs. The study demonstrates that system-level tools employing simple heuristic and analytic models, alongside midrange tools that operate with standard architectural simulators, are essential for characterizing a range of designs. The report showcases the PIM Lite chip as a case study, illustrating that implementations using regular patterned "bricks" technology can achieve performance comparable to conventional ASICs while maintaining a design flow that is only slightly more complex.

    The document also discusses the benefits of the developed design methodology, which not only aligns with the manufacturing processes of dense memory but also facilitates high-level design space exploration, thereby reducing both front-end and back-end design costs. The findings suggest that further research with more complex reference designs could provide deeper insights into potential savings in design time and costs.

    In conclusion, the report emphasizes the importance of patterned ASICs and recommends follow-on work to explore this area further. It serves as a valuable resource for understanding the advancements in ASIC design methodologies and their implications for future technology development. The report is approved for public release and is available for dissemination, contributing to the broader scientific and technical information exchange.

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