Implementing On-Board Cloud Detection on a Reconfigurable Computer

RCs combine traditional microprocessors with FPGAs to enable on-board processing of cloud contamination for satellite remote sensing.

Reconfigurable Computers (RCs) combine traditional microprocessors with field programmable gate arrays (FPGAs), and are characterized by lower form/wrap factors compared to parallel platforms. Therefore, RCs are a promising candidate for on-board preprocessing. The RC used in this real-time cloud detection system is an SRC-6E reconfigurable computer. The system can be used for on-board preprocessing by prototyping the Landsat 7 ETM+ ACCA algorithm on the SRC-6E.

The Hardware Architecture of the SRC MAP processor. This processor consists of two programmable FPGAs, six 4-MB banks of the on-board memory (OBM), and a single control FPGA.
The Landsat 7 ETM+ ACCA algorithm is based on the observation that clouds are highly reflective and cold. The high reflectivity can be detected in the visible, near-, and mid-IR bands. The thermal properties of clouds can be detected in the thermal IR band. The Landsat 7 ETM+ ACCA algorithm recognizes clouds by analyzing the scene twice. In the first pass, six filters are utilized for this purpose. The goal of pass one is to develop a reliable cloud signature for use in pass two, where the remaining clouds are identified. Commission errors, however, create algorithm failure and must be minimized.

Three categories result from pass one: clouds, non-clouds, and an ambiguous group that is revisited in pass two. In pass two of the algorithm, descriptive statistics are calculated from band 6 to describe the cloud category: these include mean temperature, standard deviation, and distribution skew. New band 6 thresholds are developed from these statistics. Only the thermal band is examined during pass two in order to capture the remaining clouds. Image pixels that fall below the new threshold qualify as cloud pixels. After pass two processing, cloud cover results from both pass one and pass two are compared. Extreme differences are indicative of cloud signature corruption. When this occurs, pass two results are ignored and all results are taken from pass one.

During processing, a cloud mask is created. After the two ACCA passes, a filter is applied to the cloud mask to fill in cloud holes. This filtering operation works by examining each non-cloud pixel in the mask. If five out of the eight neighbors are clouds, then the pixel is reclassified as cloud. The final cloud cover percentage for the image is calculated based on the filtered cloud mask.

The SRC-6E platform consists of two general-purpose microprocessor boards and one MAP reconfigurable processor board. Each microprocessor board is based on two 1-GHz Pentium III microprocessors. The SRC MAP board consists of two MAP reconfigurable processors.

Overall, the SRC-6E system provides a 1:1 microprocessor to FPGA ratio. Microprocessor boards are connected to the MAP board through the SNAP interconnect. SNAP card plugs into the DIMM slot on the microprocessor motherboard. The SRC MAP processor consists of two FPGAs, six 4-MB banks of the onboard memory (OBM), and a single control FPGA. The FPGAs are Xilinx Virtex II-6000-4. The SRC-6E has a similar compilation process as a conventional microprocessor-based computing system, but needs to support additional tasks in order to produce logic for the MAP reconfigurable processor.

The ACCA algorithm adapted for Landsat 7 ETM+ data has been implemented both in C and MATLAB, and pass one has been implemented and synthesized for the Xilinx XC2V6000 FPGA on SRC-6E.

The only constraint to the design was the processing speed, as measured by throughput. This constraint is approached through full pipelining of the design. Many of the tests in pass one are threshold tests of ratio values, such as the snow test. It was more efficient, in terms of the required resources, to multiply one value by the threshold, and compare with the other value, instead of performing the division then comparing against the threshold.

The design was developed in VHDL, synthesized, placed, and routed, and was found to occupy approximately 7% of the available logic resources on the chip. This enabled instantiation of eight concurrent processing engines of the design in the same chip, which increased the performance eight-fold. The total resources utilization for the eight-engine version was approximately 57. The maximum operational clock speed of the design is 100 MHz, which resulted in 4000 Megapixels/sec. (5 inputs × 8 engines × 100 MHz) as data input/consumption rate. The data output/production rate was 800 Megapixels/sec. (1 output × 8 engines × 100 MHz).

This work was done by Esam El-Araby, Mohamed Taher, and Tarek El-Ghazawi of The George Washington University; and Jacqueline Le Moigne of NASA’s Goddard Space Flight Center.


This Brief includes a Technical Support Package (TSP).
Document cover
Implementing On-Board Cloud Detection on a Reconfigurable Computer

(reference GWU-0001) is currently available for download from the TSP library.

Don't have an account? Sign up here.