Open Generic Avionics Architectures and Distributed Processing Using Ethernet and VPX
The backplane and hardware module standards help to increase part commonality and the reuse of components in different system architectures and applications, but this is only one part of the system design challenge. While the specified footprint, backplane format, and electrical signal characteristics help the design of modular hardware and open architectures, they still tell very little about how modular (and unambiguous) the interfacing among functions and their interactions are. This aspect is covered at the system integration (network) layer.
VPX, as a switched fabric, supports the design of advanced integrated systems using technologies such as deterministic Ethernet, which can be used in backplane and backbone applications. In cases where functional interrelationships and Ethernet network bandwidth sharing is deterministic and all logical links among critical function have configurable quality of service with guaranteed timing, the complexity challenges in design of advanced integrated architectures can be much simpler to handle and mitigate. This enables design of truly open and flexible modular embedded systems, which can host hard real-time, real-time, and soft functions at lower system lifecycle costs. Incremental modernization is fully supported, and new functions can be added without influencing already integrated ones.
VME and the VPX Market
VME has been used for over 30 years in different industries, and its latest VME64 64-bit backplane can move 40MByte of data per second between plugged cards. Over the years, many extensions have been added to the VME interface (VME64x), providing “sideband” channels of communication in parallel to VME itself, to enhance bandwidth capabilities.
VPX (ANSI/VITA 46.0-2007) is positioned as a VME successor and backplane standard for design of rugged modular systems, designed by the VITA and its 100+ members. The VME embedded market today in aerospace and defense applications is estimated to be $600M (~20% is VPX). The difference in market numbers comes from the fact that VME boards are used for upgrades to existing systems, while VPX is used in new designs.
The VPX standard enables integration of high-speed serial switched fabric interconnects such as PCI Express, RapidIO, Infiniband, and 10 Gigabit Ethernet to satisfy high bandwidth requirements in a minimized footprint. Around this VITA (www.vita.com) standard, an ecosystem of COTS products has developed since 2008, with over 400 board products provided by major COTS board suppliers, such as Curtiss-Wright, GE IP, Kontron, Mercury, and over 30 other suppliers.
VITA 68 Bandwidth Extensions for VPX Backplane
As VPX was designed, the network bandwidth was significantly lower for many of the networking technologies used only 7-8 years ago. VITA 68 was introduced to support the integration of extended bandwidth and integrity guarantees for high-bandwidth networks into the VPX backplane format.
VITA 68 defines a VPX compliance channel, including common backplane performance criteria, required to support multiple fabric types across a range of defined baud rates and bit error rates (BER) for different fabric types. With this standard, the latest Ethernet physical layers (1000T-KX, 10GT-KX4), sRIO (6.25Gbps), Infiniband DDR (5Gbit/s) and QDR (10Gbit/s), and future technologies (100Gbps Ethernet 802.3bj) are and can be supported in VPX. The excess bandwidth does not assure deterministic operation, but new high-bandwidth Ethernet variants with 10+ Gbps and Layer 2 QoS extensions can enable the design of deterministic distributed functions and well-defined use of shared networking resources.
In the VPX standard, there is the difference between extension plane (PCIx, S-ATA, ...), control plane (Gigabit Ethernet), data plane (Inifiniband, serial RapidIO( sRIO), 10G Ethernet), and utility plane (clock sync, power …). In Figure 1, a logical view of inter-module connectivity and integration with Ethernet VPX backplane and backbone is presented.
While InifiniBand and sRIO offer high bandwidth for distributed processing of large data volumes, they do not provide temporal guarantees for design of real-time systems. With Gigabit-Ethernet at a control plane, it is also not trivial to design hard RT systems and ad vanced integrated architectures. However, with Gigabit-Ethernet switches, which support deterministic QoS Layer 2 services, VPX plays the role of key platform technology for the design of advanced integrated systems with time-critical (hard RT), mission-critical, and safety-critical systems, which are simpler to design, integrate, maintain, verify, certify, and reuse. Essentially, the deterministic Gigabit-Ethernet switching devices for VPX backplane are not different from any standard Ethernet switch. Critical functions can take advantage of QoS services, while for all other less critical functions the network operates as any other switched Ethernet network.
VPX Ethernet Switches for Deterministic, Hard Real-Time Applications
While the electrical and mechanical aspects of the VPX backplane standard are known at the component level to many engineers, its capabilities and support for the design of advanced integrated architectures with deterministic and hard real-time applications have been rarely discussed in technical publications and press. It is believed, even among market analysts, that the older VME variant is more suitable for real-time applications than VPX. However, the fact is that VPX relies on serial switched fabrics, quality-of-services, (QoS) and its real-time performance. The system based on VPX is as (hard) real-time as the underlying backplane “databus” technology. VPX switches with ARINC664 and SAE AS6802 services enable deterministic integration of many critical functions hosted on common embedded computing and networking resources. The comparison is provided in Table 1.
Deterministic Ethernet and Layer 2 QoS Enhancements
Layer 2 QoS enhancements provide traffic classes that can handle Ethernet traffic with well-defined temporal properties (latency and jitter control). The determinism of communication can be defined as a maximum point-to-point latency. For demanding hard RT behavior and processes with >Nx1000Hz sampling cycles, the determinism can be defined as a fixed latency, jitter controlled with μs-precision, and known message order. Another reason why the jitter should be controlled in complex integrated systems is the embedded virtualization.
In a distributed real-time computer with hosted hard RT functions, along with less critical functions for diagnosis, health management, and bulk data transfers (e.g. recording, A/V), the access to all resources shall be predefined in order to protect the performance for critical functions. The availability of fault-tolerant system time can simplify the virtualization.
ARINC664 is an Ethernet traffic class that provides defined maximum latencies for any periodic unicast/multicast data stream in the system. This is accomplished by per-stream traffic shaping and policing. The technology is used in integrated modular architectures for commercial aircraft and military transporters, such as the Boeing 787, Airbus A380, Airbus A350, Airbus A400M, and many others. All new aircraft use AFDX (ARINC664) networks to reduce SWaP.
SAE AS6802 is an Ethernet traffic class that provides fixed latencies for any periodic unicast/multicast data stream in the system, unaffected by other less critical traffic load. This service also provides a fault-tolerant distributed timebase used by different computing modules in the network, and/or Ethernet devices for scheduled forwarding of data.
With SAE AS6802, Ethernet gains strictly deterministic synchronous communication capability and can emulate circuit-switching communication in packet-switched Ethernet networks. Figure 2 shows the position of this service in the OSI layer model with relation to other Ethernet layers and applications. SAE AS6802 services do not depend on bandwidth or distance — they can operate at 0.1 to 10 Gbit/s or higher and can be used in large networks. Together with other QoS enhancements, Ethernet fully supports synchronous and asynchronous communication.
With SAE AS6802, system functions can be integrated on a common shared infrastructure and scheduled for all critical functions. All other bandwidth can be used for less critical applications.
Both ARINC664 and SAE AS6802 services do not modify operation of existing Ethernet services and are compliant with all standard Ethernet physical layers for backbone and backplane networks, including those described in VPX (VITA 46) and VITA 48. They are also compliant with higher OSI Layers 3-6.
Ethernet — As Deterministic as MIL-1553
With SAE AS6802 services, Ethernet networks can gain deterministic performance comparable to TDMA communication networks (e.g. MIL-1553 in synchronous communication mode, or Time-Triggered Protocol (TTP) – SAE AS6003), but at much higher communication speed, without bus controller and in complex switched architectures. It enables strictly deterministic communication, fixed latency, sub-μs-jitter, and predictable message order in redundant multi-hop networks. Layer 2 Quality of Service (QoS) enhancements, standardized as Time-Triggered Ethernet (SAE AS6802), guarantee deterministic computing and networking performance for advanced integrated systems. MIL-1553 operation can be emulated over an Ethernet network that implements SAE AS6802.
SAE AS6802 “Time-Triggered Ethernet” is used for human-rated space flight (NASA Orion), and evaluated for different aircraft and rotorcraft systems. It is used for the design of systems that utilize unified networking and support integration of hard real-time, real-time, and soft-time functions.
Advanced Integrated Architectures
Different variants of generic open architectures can be implemented by using VPX-based Ethernet backplane and backbone networks, assuming they provide absolute temporal guarantees and determinism for different critical functions (Figure 3).
Control-plane applications in VPX typically use single- or dual-star (redundant) topology with switched Gigabit Ethernet, which are also supported by VPX switches with SAE AS6802 QoS (TTEthernet switch). Depending on the application, TTEthernet switches can be used for control plane, data plane, and some utility plane applications (synchronization) in VPX-based systems. This means all functions and modules connected to backplane and backbone networks operate as if they are connected directly to a large, fault-tolerant Ethernet backbone. By allowing robust TDMA partitioning of networking resources, the system designer can determine the level of integration/interaction or isolation among different functions. This enables the design of innovative architectures and distributed platforms that can host many distributed functions using shared computing/ networking resources for advanced integrated system architectures.
In deterministic Gigabit-Ethernet networks, it is possible to emulate reflective memory by using a periodic global data exchange with applications that are synchronized to the global timebase generated at the network level by SAE AS6802 services. From the logical perspective, different distributed functions gain a private, congestion-free shared memory. By using this approach, we can scale the level of functional integration without influencing other existing functions in the system. Also, distributed applications do not need to know about underlying architecture or topology.
Therefore, sensor fusion and distributed payload processing can be executed without fear of unintended interactions with other system functions. Voting on data from synchronous sources simplifies redundancy management and application software design. Obsolescence management, modernization, and upgrades with new DSP processors and applications are simplified, as the behavior of already integrated functions will not change and cause new system integration or timing issues. Critical, hard real-time functions will not be influenced by other less critical distributed functions. Sensor front-end data can be streamed to platform systems or common core computing systems, with exact latency and no jitter, independent of network load. This also means that processing functions do not require spatial proximity to a specific sensor, and can be placed anywhere in the system. This also simplifies reconfiguration, upgrades, and incremental modernization.
VPX modules and VPX-based Ethernet switches like those shown in Figure 4, which implement SAE AS6802 and ARINC664 and support Gigabit (or higher) bandwidth, support the design of open generic architectures in which the operation and interaction of all critical functions can be defined at design time, and new functions can be integrated with minimal impact on existing ones. This significantly reduces costs and effort in all phases of system lifecycle, and allows integration of robust hard RT functions in integrated embedded systems hosting safety-, time-, and mission-critical functions. Here-with, the design of integrated modular architectures, which follow key objectives of MOSA (Modular Open System Acquisition) and IMA DO-297 (Integrated Modular Architectures – Design Guidance and Certification Consideration), can be applied in complex Ethernet and VPX-based embedded systems.
This article was written by Mirko Jakovljevic, Senior Marketing Manager, and Perry Rucker, Director of Sales, TTTech North America Inc. (Andover, MA). For more information, Click Here .