Designing Thermal Management Systems for Smaller, Lighter Avionics

The avionics systems of military aircraft support maneuverability and situation awareness for the pilot, process essential images, operate sensors, record data, and provide for broadcast and communication between home base and wingman. The newest generation of military aircraft cannot be flown without avionics, and modern combat is making the leap to electronic warfare.

Figure 1. Die-attach voids shown in the derivative of the structure function<sup>1</sup>.

New processors and other electronic components are smaller, faster and more powerful. But with these advances, power density increases, making thermal management essential to ensure the reliability of these components. An electronic failure in mid-air is simply not an option.

As more electronic components are incorporated into aircraft designs, they become heavier. More weight can mean less time in the target zone. Thus, the tradeoff of size, weight, and power (SWaP) is a crucial system design consideration.

Lifetime Testing and Failure Characterization

High reliability of safety-critical components is important to ensure perfect functioning of a system over its lifetime. A lifetime may be several thousand hours under constantly changing conditions such as temperature variations and shocks, pressure variations, humidity, etc., which increase the aging process resulting in component or material failures. Methods such as highly accelerated life testing (HALT), in which components are exposed to harsh environments worse than the actual environments to accelerate the aging process and pinpoint degradation, shortens the original testing time.

Figure 2. Test set with two failures show in the derivative of the structure function, a) die-attach delamination in the package, b) imperfect package soldering.

Thermal characterization is a nondestructive measurement and can reveal failures inside the component. If the die attach is degrading and the die is delaminating, for example, thermal resistance will rise, which increases the junction temperature of the component because the heat isn’t dissipating efficiently anymore. As a result, the component is likely to fail sooner than a healthy component because excessive temperature over a long time accelerates the aging process.

The following examples illustrate different failures in a component in general and during the aging of the component. The structure function clearly shows increased thermal resistance of the component for these failures (Figures 1 and 2).

Failure in the package structure and in the heat path outside the structure can be measured up to the environment. The rest of the structure function, depending on the magnitude of the failure, is often just shifted horizontally or vertically, which indicates that the rest of the heat path has kept its properties and the failure only exists in the responsible layer of the package or assembly.

When different LEDs were compared over a lifetime of up to 6,000 hours, a set of LEDs failed after around 3,000 hours compared to some LEDs that reached 6,000 hours without substantial degrading of the components2.

The LEDs of one product degraded just slightly, which was possibly caused by a delamination of the LED package from the printed circuit board (PCB). Another product had an even more significant degradation of the TIM between 0 and 500 hours.

Figure 3. In situ thermal characterization of a DRAM chip on the module and motherboard of a PC in a JEDEC still-air chamber.

If a cold plate is used for a better fixed “environment” temperature, thermal characterization of components soldered onto PCBs can be measured quickly. For measurements in a complete system, the measurement can take longer because it is often hard or impossible to fix the temperature to a certain value and achieve a faster convergence to the cold steady state of the measurement. If proper cooling can be applied to the system, it can accelerate the measurement.

In addition to the overall system, other components, larger PCB, etc. will also influence the measuring time—the heat has to reach the hot and then cold steady state and all components influence this process with their own heat capacity.

In general, a complete system can be measured and thus, maintenance work on the aircraft’s system is possible. Such an in situ measurement of a system is shown in Figure 3, which is an example of a memory chip on a dynamic random access memory (DRAM) module on a PC motherboard in a Joint Electron Devices Engineering Council (JEDEC) standard still-air chamber.

Using Standardized Testing to Compare Quality

Figure 4. Cooling curve of a sample component.

The Mentor Graphics T3Ster® thermal transient tester uses a “smart” implementation of the static test version of the JEDEC JESD51-1 electrical test method3 that allows for continuous measurement during a heating or cooling transient. This measurement methodology for the junction-to-case thermal resistance of power semiconductor devices makes it possible to thermally characterize a component with high accuracy and repeatability. The result is far richer data that is measured from much earlier in the junction temperature transient than possible with other techniques. The automatically generated compact thermal model of the component can then be applied directly in computational fluid dynamics (CFD) simulation software.

The T3Ster post-processing software fully supports the JESD51-14 standard for junction-to-case thermal resistance measurement4, allowing the temperature versus time curve obtained directly from the measurement to be re-cast as “structure functions” (described in JESD51-14 Annex A), and then easily find the value of the junction-to-case thermal resistance.

The characterization method uses the temperature sensitivity of the semiconductor component. This sensitivity has to be measured before the actual characterization can begin, and it should be done according to the JESD51-13 standard to record the cooling curve of the component.

Once the measured temperature sensitivity parameters (TSP) are obtained, the component can be characterized by powering up the device (heating it) with PH [Watt] until a steady state is reached. Once the junction temperature TJ is constant, the heating current is switched off to a lower measuring current that creates a low measuring power PM [Watt]. The measuring current is negligible compared to the heating current. This sharp power step introduces the cooling process and is recorded until a steady state is reached.

Figure 5. Structure function of a sample component showing vertically thermal capacitance and horizontally thermal resistance.

From the temperature sensitivity of the component and the lower steady state temperature, ideally realized with a cold plate, the transient cooling curve is created as shown in Figure 4. The temperature difference T [Kelvin] is derived by the temperature sensitivity of the component, and the thermal resistance of the component can be calculated as shown in the equation:

Rth = ΔT/(PH - PM).

From the recorded cooling curve, a structure function can be derived as shown in Figure 5. This structure function shows thermal resistance and capacitance of the single layers from junction to environment. The vertical sections of the curve show thermal capacitance Cth [W/(s·K)] and low thermal resistance Rth [K/W] materials such as metallic layers in the component structure; whereas horizontal lines show higher thermal resistance layers such as die attach, glue, grease, and other TIMs and PCB layers, etc.

Each step of the structure function can then be described as a resistor and capacitor in a Cauer ladder as shown in Figure 6. By specifying the final node “case” of the component in the curve, a compact thermal model can be derived and used for accurate component representation in a simulation for the thermal resistance from junction to case.

Using CFD to Design a Better Avionics Cooling System

Engineers at Tecnobit used Mentor Graphics’ FloTHERM CFD software to help them understand and optimize the different heat transfer paths and mechanisms between electronic components and the ambient surroundings found in aircraft.

Figure 6. Step by step from component to Cauer ladder.

They designed a special chassis enabling the avionics to be housed in a reduced space (maximum dimension close to 10 cm). The system was totally sealed, so the task was to maximize heat transfer by conduction, radiation, and natural convection at the outside surface. The preliminary design was not thermally acceptable, so they modified the internal chassis structure to increase heat conduction from the components to the chassis walls. They also modified the outer surfaces of the chassis using special fins, sand blasting treatment, and electrostatic painting to enhance convection and radiation exchange with the external ambient.

By using CFD, they were able to save time and money because no time was wasted building unfeasible prototypes, and the CFD simulations enabled them to optimize the thermal design rapidly and reduce component junction temperatures by 40 °C compared with the initial design.

This article was written by Boris Marovic, Product Marketing Manager for Aerospace and Defense, Mentor Graphics Corporation (Frankfurt, Germany). For more information, Click Here .


  1. M. Rencz, V. Székely, A. Morelli, C. Villa, “Determining partial thermal resistances with transient measurements and using the method to detect die attach discontinuities,” 18th Annual IEEE SEMITHERM Symposium, March 1-14 2002, San Jose, CA,USA, pp. 15-20.
  2. András Poppe, Gábor Molnár, Péter Csuti, Ferenc Szabó, János Schanda, “Ageing of LEDs: A comprehensive study based on the LM80 standard and thermal transient measurements,” CIE 27th Session- Proceedings, CIE 197:2011: (Volume 1, Part 1-2), Sun City, South Africa, 10/07/2011-15/07/2011, Vienna, CIE, pp.467-477, Paper OP57 (ISBN: 978 3 901906 99 2).
  3. JEDEC Standard JESD51-1, “Integrated Circuit Thermal Measurement Method – Electrical Test Method (Single Semiconductor Device),”, JEDEC, Dec. 1995.
  4. JEDEC Standard JESD51-14, “Transient Dual Interface Test Method for the Measurement of the Thermal Resistance Junction-To-Case of Semiconductor Devices with Heat Flow through a Single Path,” results/JESD51-14, JEDEC, Nov. 2010.