Microchip’s New Processor Enables Scalable Computing Performance

March 1, 2026

Microchip’s PIC64 is a new portfolio of microprocessors that the Chandler, Arizona-based company claims could enable a generational leap in embedded processing performance for aerospace and defense applications.

The new MPU technology is supported by a 64-bit reduced instruction set computer (RISC-V) architecture with an embedded Time Sensitive Networking (TSN) Ethernet switch.

What is the PIC64 microprocessor and how can it advance embedded computing performance for a wide range of aerospace and defense applications? Check out our Q&A session with Bill Dillard, Senior Manager of Aerospace and Defense at Microchip, from his interview featured on the Aerospace & Defense Technology podcast .

Aerospace & Defense Technology (A&DT): Considering your company’s history… how have recent DoD acquisition changes affected how you supply this market?

Bill Dillard: We’re seeing a new generation of defense customers — often privately funded companies — who are able to move much faster than the traditional prime contractor model. The DoD is prioritizing speed and reducing development budgets, which forces customers to accelerate their development cycles and design with reuse in mind rather than aiming for a “perfect” solution every time.

Microchip’s MPU family meets mid-range intelligent edge compute needs with a 64-bit RISC-V® quad-core processor offering asymmetric multiprocessing and deterministic latencies. It features a configurable processor and memory subsystem to support secure boot and key management for military-grade security. (Image: Microchip)

To support this shift, we’ve adapted our approach to match the pace our customers need. During the development phase, we provide rapid technical support, evaluation boards, and other resources so they can move quickly.

Once their systems reach the market and begin generating revenue, their needs shift toward stability. At that point, our role becomes offering a highly reliable, long term supply chain. This two-pronged approach — speed during development and stability in production — has resonated with both our long time prime customers and the newer fast moving entrants.

A&DT: What is PIC64, and how does it compare performance-wise to your previous generation of multi-core processors?

Dillard: When we developed PIC64, we set out to deliver a true generational leap forward for both our customers and Microchip. Several core principles guided the design.

This is the PIC64GX microprocessor unit (MPU). Typical Symmetric Multiprocessing (SMP) implementations may offer the flexibility of a rich operating system but are terrible for running real-time systems that need deterministic performance. PIC64GX MPUs feature a multi-core Linux OS-capable processor that is coherent with the memory subsystem, allowing a versatile mix of deterministic real-time systems and the Linux OS in a single multi-core CPU cluster. (Image: Microchip)

First, we wanted powerful asymmetric multiprocessing, allowing multiple operating systems to run simultaneously on separate cores. For example, one core can act as a hypervisor coordinating Linux and other OS instances side by side.

Second, we focused on dramatically improving edge computing performance — by at least a factor of 10. PIC64 is designed to sit as close as possible to mission activity such as sensors or cameras, providing real time, embedded processing rather than functioning like a traditional desktop style computer.

Third, we emphasized post quantum security. PIC64 includes advanced cryptography, secure boot, anti tamper features, and other protections aligned with emerging standards.

Finally, we built in high value connectivity. In space and defense markets, Ethernet capability is essential, so PIC64 incorporates TSN (Time Sensitive Networking) protocols. One device in the PIC64 family includes an integrated 16 port, 240 gigabit Ethernet switch. That significantly reduces system component count — you can remove a separate switch from the bill of materials — and provides extremely high data throughput.

A&DT: Certification of multi-core processors for avionics has been historically difficult. How does PIC64 address those challenges?

Dillard: Certification has always been challenging because agencies like the FAA are rightly concerned about how multiple cores share resources such as cache memory. If one core’s activity interferes with another’s, it could produce undetected errors — something unacceptable in safety critical avionics.

Microchip has made this low-cost PIC64GX Curiosity Evaluation Kit available to developers for rapid evaluation of MIPI CSI-2®, HDMI®, SPI, I2C, QSPI, DDR, microSD and Ethernet applications. (Image: Microchip)

PIC64 tackles this through deep configurability. Its eight-core architecture can be arranged as eight independent cores, four paired cores, or two groups of four. Pairing cores enables lockstep operation, where two cores run the same code at the same clock speed and compare results cycle by cycle. This dramatically reduces the chance of undetected errors and supports DAL A (Design Assurance Level A) certification paths.

Another key feature is WorldGuard, which allows designers to allocate specific shared resources exclusively to a given core. That effectively creates isolated microprocessor subsystems within the chip — ideal for the most safety critical functions. Less critical tasks can share remaining resources under hypervisor or system manager control. This level of isolation and configurability gives system architects powerful tools for managing reliability and mixed criticality workloads.

A&DT: What defense applications do you expect PIC64 to enable in the near future?

Dillard: One of the most promising areas is autonomy, which relies heavily on edge computing. PIC64 can be placed right at the sensor edge to ingest and process data quickly, then push results out over TSN Ethernet for time sensitive communication.

While many people immediately think of drones or drone swarms, autonomy in the military is much broader and still in its early stages. The algorithms, hardware requirements, and overall system architectures are evolving rapidly. Because of its processing capability, security features, and connectivity, PIC64 is drawing strong interest from programs exploring these next generation autonomous systems.

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