Microchip’s New Microprocessor to Enable Generational Leap in Spaceflight Computing

September 1, 2024

Microchip is launching a new class of microprocessors (MPUs) that the company claims will provide a generational leap in the computational performance of spacecraft avionics. The new family of PIC64 High-Performance Spaceflight Computing (HSPC) MPUs are among the first new line of MPUs developed specifically for the radiation and fault-tolerant challenges presented by operating computers inside of satellites and other spacecraft on low Earth orbit (LEO) and deep space or planetary exploration missions in more than 20 years, according to the Chandler, Arizona-based computing chip maker.

Developed under a 2022 $50 million contract awarded to Microchip by NASA, the PIC64-HPSC MPUs contain most of the interfaces, embedded software, networking and support for artificial intelligence and machine learning that have previously not been widely available for space avionics systems. Microchip has also established an early ecosystem of embedded computing and software partners that have all of the necessary components and features necessary to eventually provide spaceflight ready computing hardware within the next 1-2 years.

Supported by a 64-bit reduced instruction set computer (RISC-V) architecture with an embedded Time Sensitive Networking (TSN) Ethernet switch, the new family of microprocessors provides the embedded computing foundation necessary to enable next generation spacecraft to perform a variety of data-intensive missions. Microchip’s inclusion of the RISC-V architecture and the embedded TSN Ethernet switch are key components of the generational leap in computational performance. TSN specifically has been an embedded networking capability that a growing number of aerospace and defense original equipment manufacturers (OEMs) desire to include in new aircraft, ground vehicles and other assets, in addition to the spacecraft computers Microchip is focused on with PIC64.

In its “High Performance Spaceflight Computing” white paper published July 24, 2024, NASA provided a deeper explanation of why Microchip’s new MPU will enable significant advances in onboard spacecraft computing including navigation and control systems, complex science instruments, robotic science sample acquisition and return, communications, autonomous robotic operations, among others. The agency also explains why TSN Ethernet and RISC-V are critical elements of the new MPU.

RISC-V, according to NASA’s white paper, is a 64-bit open standard Instruction Set Architecture (ISA) that features a small core set of instructions upon which a processor’s software runs. As an open-source ISA, RISC-V allows designers to build their processing modules in a way that is customized and tailored to their target end applications, so they can optimize the power, performance, and area for those applications. Including RISC-V will also help optimize the size, weight and power (SWaP) of future spacecraft computers.

“RISC-V vectors are a powerful and super-efficient extension that features compact code size, high performance capability and the on-die [System on Chip] SoC structures consume a limited area compared to Single Instruction Multiple Data (SIMD) architecture approaches favored by other ISAs,” NASA writes in the white paper.

In the company’s press release announcing the launch of the PIC64 MPUs, Microchip notes that the vector-processing instruction extensions included in the PIC64 MPU are configured specifically to support artificial intelligence and machine learning (AI/ML) applications.

Microchip’s inclusion of a TSN Ethernet switch on PIC64 could be a game changer for designers of next generation spacecraft computing networks that need to allow multiple subsystems to transmit and receive data at varying levels of criticality. Compared to the older networking protocols featured on the majority of in-service or operational spacecraft, the use of TSN allows data to be distributed between subsystems and devices in a deterministic fashion, meaning traffic is scheduled, predictable and traffic from systems that are more critical to a spacecraft’s mission success could be separated from other less pertinent systems.

Developed by the IEEE 802.1 working group, TSN is a newer set of standards and features that provide an embedded computing framework that can enable deterministic messaging and real-time data communication over an Ethernet network, according to the Cisco white paper, “Time-Sensitive Networking: A Technical Introduction.” Among the features within TSN that enable deterministic messaging and real time communication are traffic scheduling algorithms that help system designers prioritize time critical data messaging and traffic. The overall goal of using TSN Ethernet is to guarantee synchronization and separation of real-time traffic for safety critical systems from less critical systems traffic.

IEEE and SAE are currently working on the definitions for TSN Aerospace profiles in the SAE AS6675 Working Group as IEEE 802.1DP. The 240 Gbps TSN Ethernet switch featured in the PIC64 has an attached Remote Direct Memory Access (RDMA) feature developed using the RDMA over Converged Ethernet (RoCE) version 2 standard, according to NASA’s HPSC white paper. The combined capabilities of the RDMA and TSN switch will allow spacecraft computers to “ingest high-bandwidth sensor data and support the creation of HPSC purpose built or ad hoc processing clusters to work on larger science problems,” NASA writes in the white paper.

During a media briefing with Aerospace Kevin So, Head of Product Line Management, Microchip and Tao Lang, Senior Manager of Product Marketing for Microchip’s communications business unit, explained how their new 64-bit multicore MPU is among the first upgrades for space avionics MPUs in more than 20 years.

“We want to try to modernize the space computing industry,” Lang says. “The space-ready processors that are available on the market today use very old architectures. They’re using PowerPC, some are even using Spark, these legacy architectures and interfaces that you almost would not even find in the commercial world today. Legacy interfaces like SpaceWire, which is something that’s dedicated only to the space industry, are still in place. We wanted to try to bring the modern commercial CPU to the space industry.”

PIC-64-HPSC MPUs will come in two different versions for the space sector including a radiation hardened version for LEO operations where system providers often prioritize low cost. Both Lang and So said there will also be versions of the PIC64 developed for broader aerospace and defense applications such as aircraft and ground vehicles among others.

Microchip, as previously stated, has already begun establishing an ecosystem of embedded computing and software providers capable of providing every component and software application necessary to design a spaceflight computer system anchored by the PIC64-HPSC MPU. Early ecosystem partners include a total of 18 safety critical or real time operating system (RTOS) software providers, including several that already provide an extensive amount of safety critical software to the aerospace and defense industry. On the software side, Microchip has partnered with Wind River, Green Hills, Linux, Sysgo and OpenSSL among others. Infineon and Teledyne e2v are among the components suppliers within the new ecosystem, while Moog, IDEAS-TEK and Ibeos are among the earliest board vendors to join the ecosystem.

“Microchip’s PIC64-HPSC family replaces the purpose-built, obsolescence-prone solutions of the past with a high-performance and scalable space-grade compute processor platform supported by the company’s vibrant and growing development ecosystem,” said Kevin Kinsella, Architect - System Security Engineering with Northrop Grumman. “This innovative and forward-looking architecture integrates the best of the past 40-plus years of processing technology advances. By uniquely addressing the three critical areas of reliability, safety and security, we fully expect the PIC64-HPSC to see widespread adoption in air, land and sea applications.”

Microchip is making PIC64-HPSC samples available to “early access partners” next year, as confirmed by the two engineers who provided the briefing on the launch of their new MPU family. The company is planning on offering a PIC64-HSPC evaluation platform evaluation platform that includes the MPU, an expansion card and a variety of peripheral daughter cards.

In a statement published by NASA shortly after Microchip’s launch of its new MPU family, Dr. Prasun Desai, Deputy Associate Administrator, NASA, summarized the agency’s anticipation of what future space missions that the new processors could support.

“The project will spur innovative solutions for next generation space computing tailored to different mission applications that the whole world can harness. Advancing this capability will transform future space missions at a rapid pace,” he said. “It is truly a game changing technology advancing the current state of the art capability by up to 100X, and it is very exciting as we get closer to manufacturing the processor.”

This article was written by Woodrow Bellamy III, Senior Editor, SAE Media Group (New York, NY).

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