AC Coupled Interconnect for Low-Power Spaceborne Electronics

This technology could reduce the power consumed in high-speed memory buses.

February 1, 2009

Air Force Research Laboratory

An AC coupled interconnect (ACCI) has been developed that could be used to create multiple solutions to contactless chip-to-chip communications. Assembly and testing of a 0.18 um bulk CMOS chip containing multiple circuit experiments were performed. Figure 1 shows the chip floorplan, chip layout for the wire bonded experiments, and a microscope photograph of the die. The experiments tested in this phase of measurements were located around the periphery of the die in the band designated in the die photo of Figure 1.

Figure 1. The ACCI Chip floorplan, chip layout for the wire bonded experiments, and a microscope photograph of the die are shown.

A 6-bit wide ACCI bus was demonstrated, which operates at 36 Gbps or 6 Gbps/channel, over 30-cm transmission lines on FR4, with transceiver power dissipation less than 2 mW/Gbps, while subject to crosstalk and switching noise from the simultaneous operation of six channels. Additional signal integrity analysis was performed to ensure it was robust to crosstalk noise and simultaneous switching noise.

Figure 2. A scaled prototype of an Inductively Cooled Connector, and a 250-Mhz eye diagram.

Two different inductively coupled systems were designed, one for single-coupled systems, and another for dual-coupled systems. Several versions of the circuits for this structure are currently in IC, MCM, and laminate fabrication. An integrated process structure was developed that can be used to build capacitively coupled laminate packages. The key enabling technology for this structure is a patternable high-K material that can be cured at the same process temperature as solder bumps. Different versions of the material can be cured to match the reflow profile for both leaded and lead-free solder.

Capacitive coupling with the capacitor formed between the chip and a package was demonstrated. Chips were built in a 0.35-μm process and flipped to an MCM substrate. The chips can communicate with each other at 2.5 Gbps over a 5-cm transmission line. Pad sizes down to 70-μm pitch were demonstrated.

Inductively coupled circuits communicating vertically through a 3D chip-stack were demonstrated. This chip was built in a 0.35-μm process and operated at 2 GHz. Communication was possible with a chip thickness of up to 120 mm. An inductively coupled connector, prototyped in a PCB technology, was demonstrated to operate at 250 MHz. Figure 2 shows a prototype and an eye diagram.

This work was done by Paul D. Franzon of North Carolina State University for the Air Force Research Laboratory. AFRL-0115