The Evolution of CompactPCI From Parallel to Serial I/O

The true worth of an industry standard is measured in its ability to stand the test of time. From the onset, the system configuration, hardware components, and integration strategy all need to be built upon the inherent principles of flexibility, modernization, and efficiency.

Figure 1. As CompactPCI has evolved, its use in various industries has grown due to its cost-effectiveness, flexibility and ease of installation.

Since the mid 1990s, CompactPCI has made a name for itself as a scalable, cost-effective and easily implemented standard that can be adapted in many ways while maintaining its true integrity, providing a uniform technology platform that benefits industries as far reaching as automation and mobile applications, as well as transportation and telecommunications (Figure 1).

CompactPCI (PICMG 2.0) originated as a parallel bus standard for building cost-effective modular industrial computers, which quickly garnered the support of a large group of suppliers covering a wide range of products from components to complete systems. It enabled applications requiring the high performance of PCI, as well as the small size and ruggedness of a rack mount system, to use a standard form factor, so OEM and end-users could directly apply PCI components and technology to a new mechanical form factor while maintaining compatibility with existing operating systems and application software available for desktop PCI.

Based on the Eurocard form factors 3U and 6U, and supporting 19" mechanics, CompactPCI was developed as a reliable, robust and maintenance-friendly technology platform. The original architecture connects the system slot to the peripheral slots and uses a passive backplane with PCI up to 64-bit/66 MHz to connect a system slot (CPU) to as many as seven peripheral slots (devices), or more with bridges.

However, recent innovations in embedded computing have begun to emphasize the importance of cost-effective technology that can meet the demands of fast serial point-to-point connections.

The Road Ahead

The development path of CompactPCI shows that the standard can be continually reinvented while maintaining the original mechanics that allow for updated versions to remain compatible with legacy systems. This is a crucial attribute to ensure that the vast installed base of CompactPCI systems remains viable and cost-effective within the many industries using CompactPCI.

According to PICMG, the industry association that maintains the standard, CompactPCI encompasses the following features:

  • Standard 3U and 6U Eurocard dimensions (complies with IEEE 1101.1 mechanical standards);
  • High density 2mm pin-and-socket connectors (IEC approved and Bellcore qualified);
  • Vertical card orientation for good cooling;
  • Positive card retention;
  • Excellent shock and vibration characteristics;
  • Metal front panel;
  • User I/O connections on front or rear of module;
  • Standard chassis available from many suppliers;
  • Standard PCI silicon manufactured in large volumes;
  • Eight slots in basic configuration easily expanded with bridge chips.

Mechanically speaking, many of these features have remained unchanged as the spec has developed, enabling newer versions of CompactPCI to match up to older components within a system. Areas with the most evolution are primarily seen in the systems’ performance and ease-of-use, such as multi-computing networking, increased reliability, and hot-swap functionality.

Most notable is the incorporation of Ethernet functionality with the PICMG 2.16 core specification in 2001 that overlaid a packet-based switching architecture on top of CompactPCI to create an embedded system area network (ESAN). It can be said that this formed the basis for the inclusion of future serial technologies required in today’s embedded computing environments.

Other ways in which CompactPCI has expanded its use is into specific application environments, such as the burgeoning telephony industry in the early 2000s and the increasing use of embedded computing systems in mission-critical, highly-reliable applications over the past decade.

These are all important factors to note in the progression of CompactPCI from its origins to the CompactPCI PlusIO and CompactPCI Serial specifications of today, because without these adaptations, CompactPCI would not have been able to keep pace with the changing embedded landscape over the past 15 years.

Connecting Old and New

The latest advancement in embedded computing is the incorporation of serial, point-to-point technology, which has generated one of the most critical evolutions in the CompactPCI standards. CompactPCI PlusIO (PICMG 2.30) and CompactPCI Serial (PICMG CPCI-S.0), both now ratified by PICMG, provide a development path for systems using CompactPCI that will avoid obsolescence for at least the next 15 years. The accompanying table clearly defines the differences in the parallel and serial interfaces of the four core CompactPCI specifications discussed.

The Pluses of PlusIO

Serial Feature Matrix

Because there is such a large community of existing CompactPCI users, careful consideration was made as to how users could maintain their existing system infrastructure when developing the latest version of CompactPCI. The solution was CompactPCI PlusIO (PICMG 2.30), where the system slot CPU supports both the legacy CompactPCI as well as the new CompactPCI Serial functions, giving designers an interim step in system development by allowing a hybrid system to exist.

CompactPCI PlusIO only defines the system slot and uses a star architecture for serial communications, since it is intended to be a simple conduit between the old and new versions of CompactPCI.

Hybrid backplanes from different manufacturers enable configuration with peripheral slot boards on the left and right of the system slot board. In addition to supporting the parallel 32-bit PCI bus, CompactPCI PlusIO supports up to seven parallel and a maximum of four serial boards — without bridges or switches — an important differentiator between the microTCA and VPX specifications also used in embedded computing, since this simplified architecture saves on both system costs and implementation requirements.

Users can inexpensively migrate to CompactPCI Serial, since the usage of future-oriented and standardized data transfer based on CompactPCI Serial is guaranteed even where integrated CompactPCI components are already used.

Getting Serious with Serial

Figure 2. With transmission speeds up to 12 Gb/s, the new connector used in CompactPCI Serial provides significantly increased data processing to meet the demands of today’s computing environments, and those to come.

As with the original CompactPCI, CompactPCI Serial (PICMG CPCI-S.0) maintains the proven 19" mechanics of the IEC 1101 as well as a dedicated system slot and passive backplane. And, like CompactPCI PlusIO, it does not need switches and bridges.

It does, however, use a configuration of one system slot and up to eight peripheral slots, and moves from CompactPCI PlusIO’s simple star architecture to full mesh for Ethernet functions.

What makes CompactPCI Serial different from its other relatives is the simple fact that it is based solely on serial technology; the parallel bus does not exist any more in pure CompactPCI Serial systems. Although it maintains much of the CompactPCI mechanics, it is defined by PICMG as a base specification, meaning that it is not merely a follow-on standard to CompactPCI and hence does not include an extension of the original 2.x designation, as CompactPCI PlusIO does in its official PICMG description as 2.30.

Geared for new installations, yet fully backward compatible with legacy CompactPCI, this standard is now the standard for systems being built on CompactPCI technology.

CompactPCI Serial, or CPCI-S.0, uses a new rugged connector with a signal density of up to 184 pin pairs (on 3U) and transmission frequencies of 12 Gb/s, exponentially increasing the data throughput and processing capabilities of CompactPCI-based systems. The connector family (Figure 2) used offers various configurations to allow for different levels of robustness.

The system slot supports eight PCI Express links (6 by 4 lanes, 2 by 8 lanes), eight SATA/SAS, eight USB 2.0/3.0 and eight Ethernet Gb/10 Gb interfaces plus signals for general system management (reset, IPMB, hot plug, geographical addressing, etc.). The pin assignment of the system and the peripheral slot is congruent, enabling a system slot board to be plugged into each peripheral slot, supporting symmetrical multiprocessing.

The Future is Now

Figure 3. A rugged, CompactPCI Serial 3U Ethernet switch featuring four Gigabit Ethernet ports via RJ45 or M12 connectors in the front, with an optional fifth port accessible at the rear via the J6 connector.

The systems, boards, backplanes, and host of other CompactPCI Serial-based embedded solutions already available from embedded manufacturers (Figure 3) show the depth and usefulness of this standard in keeping CompactPCI a viable technology platform throughout the evolution of embedded computing.

For example, new system slot cards will comply with CompactPCI PlusIO because they can also be used in a legacy CompactPCI system as system slot cards. With the rear I/O pin assignment fixed in PICMG 2.30, which was not the case in PICMG 2.0, boards from all manufacturers will work together in the system.

The door on CompactPCI is not closed. In fact, several more have been opened with the new capabilities brought in by CompactPCI Serial and its companion standard, CompactPCI PlusIO, that allow the worlds of legacy parallel-based systems and high-speed serial technology to coexist and forge new paths for the use of this cost-effective, highly reliable and time proven technology.

This article was written by Barbara Schmitz, CMO, MEN Mikro Elektronik (Nuremberg, Germany). For more information, contact Ms. Schmitz at Barbara.schmitz, or visit .